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si3406x family data sheet fully-integrated ieee 802.3-compliant poe+ pd interface and high-efficiency switching regulators with transistor bypass, sleep, wake, and led drive the si3406x family integrates all power management and control functions required in a power-over-ethernet plus (poe+) powered device (pd) application. these devices convert the high voltage supplied over the 10/100/1000base-t ethernet connection to a regulated, low-voltage output supply. the optimized architecture of this device family minimizes the solution footprint and external bom cost and enables the use of low-cost external components while maintaining high performance. the si3406x family integra- tes the required diode bridges and transient surge suppressor, thus enabling direct connection of the ic to the ethernet rj-45 connector. the switching power fet and all associated functions are also integrated. the integrated, current mode controlled switching regulator supports isolated or non-isolated flyback and buck converter topolo- gies. the switching frequency for the regulator is tunable with a simple external resistor value to help avoid unwanted harmonics for better emissions control. a synchronous driver is provided to optionally drive a secondary side fet to improve efficiency of pow- er conversion. connection to the pse switch is maintained during sleep by an optional automated maintain-power-signature (mps) signal. these devices fully support the ieee 802.3at specification for the cases of single or two event classification. standard external resistors provide the proper ieee 802.3 sig- natures for the detection function and programming of the classification mode, and in- ternal startup circuits ensure well-controlled soft-start initial operation of both the hots- wap switch and the voltage regulator. the si34061 and si34062 add main transformer bias winding support for ultra-high-effi- ciency operation. the si34061 includes support for external augmentation or full bypass of the internal hotswap and/or switching fet for best power handling and thermal management at the high end of class 4, plus offers a further boost in power conversion efficiency when needed. the si34062 includes support for sleep modes with wake function, as well as led drive capability. these features can be utilized to minimize standby current, control sleep and wake states, and provide application status information using a solid or blinking led. the si3406 is available in a low-profile, 20-pin, 5 x 5 mm qfn package, and the si34061 and si34062 are available in low-profile, 24-pin, 5 x 5 mm qfn packages. key features ? type 1 (poe) or type 2 (poe+) power ? full ieee 802.3at compliance ? synchronous secondary fet driver ? current mode dc-dc converter ? tunable switching frequency ? auxiliary transformer winding support ? auxiliary adapter support ? internal hotswap and switching fet bypass support ? automated maintain-power-signature (mps) support ? sleep mode augmented with wake pin, mode control, and led driver ? 120 v absolute max voltage performance ? extended C40 to +85 c temperature ? compact rohs-compliant 5 mm x 5 mm qfn package applications ? voice over ip telephones ? wireless access points ? security and surveillance ip cameras ? lighting luminaires ? point-of-sale terminals ? internet appliances ? network devices silabs.com | building a more connected world. preliminary rev. 0.5 this information applies to a product under development. its characteristics and specifications are subject to change without notice.
1. ordering guide table 1.1. si3406x ordering guide ordering part number package temperature range (ambient) applications si3406-a-gm 5 x 5 mm 20-qfn pb-free, rohs-compliant C40 to 85 c extended all purposes SI34061-A-GM 5 x 5 mm 24-qfn pb-free, rohs-compliant C40 to 85 c extended any high-power, high-efficiency uses, such as wireless access points and ip cameras si34062-a-gm 5 x 5 mm 24-qfn pb-free, rohs-compliant C40 to 85 c extended ip phones or other uses with sleep/green mode si3406x family data sheet ordering guide silabs.com | building a more connected world. preliminary rev. 0.5 | 2
table of contents 1. ordering guide .............................. 2 2. system overview ..............................4 2.1 block diagrams .............................4 2.2 power over ethernet (poe) line-side interface ...................5 2.2.1 surge protection ...........................5 2.2.2 telephony protection .........................5 2.2.3 detection and classification .......................6 2.3 hotswap switch .............................6 2.4 hssw state machine ...........................7 2.4.1 external hssw fet driver .......................7 2.5 dc to dc converter ............................8 2.5.1 average current sensing, overcurrent, and low-current detection ..........9 2.5.2 sync fet driver ...........................9 2.6 external hssw fet driver .........................9 2.7 tunable oscillator ............................9 2.8 regulators ............................... 10 2.9 sleep mode .............................. 10 2.10 extended sleep mode ........................... 10 2.11 external wall support ........................... 11 3. application examples ........................... 12 4. electrical specifications .......................... 14 5. pin descriptions ............................. 19 5.1 detailed pin descriptions .......................... 21 6. packaging ............................... 26 6.1 package outline: si3406 .......................... 26 6.2 land pattern: si3406 ........................... 28 6.3 package outline: si34061/62 ......................... 29 6.4 land pattern: si34061/62 .......................... 31 7. top markings .............................. 32 7.1 si3406 top marking ............................ 32 7.2 si34061 top marking ........................... 33 7.3 si34062 top marking ........................... 34 8. revision history ............................. 35 silabs.com | building a more connected world. preliminary rev. 0.5 | 3
2. system overview the following block diagrams will give the designer a sense for the internal arrangement of functional blocks, plus their relationships to external pins. the block diagrams are followed by a description of the features of these integrated circuits. 2.1 block diagrams ct1 ct2 sp1 sp2 vpos vneg detection rdet oscs fixed: 250khz adjustable: 100...500khz class & mps poe controller v11 hot-swap controller thermal protection hso 11v regulator 5v regulator rfreq vdd rcl current mode pwm controller thermal protection vss swo erout fbl fbh v11 syncl drv nsleep nt2p tvs 100v hssw 250khz 250khz vpos-1.32v vss+1.32v i bias start isns i avg dc/dc sw figure 2.1. si3406 block diagram ct1 ct2 sp1 sp2 vpos vneg detection rdet oscs fixed: 250khz adjustable: 100...500khz class & mps poe controller v11 hot-swap controller thermal protection hso 11v regulator 5v regulator rfreq vdd rcl current mode pwm controller thermal protection vss swo erout fbl v11 syncl drv nsleep nt2p tvs 100v hssw 250khz 250khz vss+1.32v i bias start isns i avg dc/dc sw vt15 aux winding support v ehssw drv exthsw v11 extgd drv swisns i pk asup figure 2.2. si34061 block diagram si3406x family data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 4
ct1 ct2 sp1 sp2 vpos vneg detection rdet oscs fixed: 250khz adjustable: 100...500khz class & mps poe controller v11 hot-swap controller thermal protection hso 11v regulator 5v regulator rfreq vdd rcl current mode pwm controller thermal protection vss swo erout fbl fbh v11 syncl drv nsleep nt2p tvs 100v hssw 250khz 250khz vpos-1.32v vss+1.32v i bias start isns i avg dc/dc sw led mode wake vt15 aux winding support figure 2.3. si34062 block diagram 2.2 power over ethernet (poe) line-side interface the poe line interface consists of diode bridges, internal surge protection, and the protocol interface support for detection and classifi- cation. internal diode bridge maximum current is given by the specification, i rect . if the application needs to consume more current from the power interface, an external diode bridge has to be used. the external bridge should be connected in parallel to the internal bridge and the designer must ensure that the internal bridge will not conduct significant current by using low-voltage-drop external diodes. the chip features active protection against surge transients and accidentally applied telephony voltages. 2.2.1 surge protection the surge protection circuit is activated if the vpos-vneg voltage exceeds t prot and the hotswap switch is off (dc-dc is not pow- ered). if the hotswap switch is on, the surge power is sunk in the dcdcs capacitance. the internal surge protection can be overridden with an external tvs if higher than specified surge conditions need be tolerated. the external surge device must be connected in parallel to the internal one; therefore, the designer must ensure that the external surge protection will activate prior to the internal surge protection. 2.2.2 telephony protection the si3406x provides protection against telephony ringing voltage. the telephony ringing is much longer than the surge pulse but it has less energy, therefore, the si3406x has a switch parallel with the supply (vpos and vneg). when the protection circuit is activated, it turns on the telephony switch; the ringing energy then dissipates on this switch and ringing generator resistance (> 400 ?). si3406x family data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 5
2.2.3 detection and classification when si3406x is connected to the ethernet cable it has to provide a characteristic resistance (~25 k) to the pse in a given voltage range (2.7C10.1 v). this is called detection. after thepse detects the pd, the pse increases the voltage above the classification threshold 14.5 v. then, the pd provides the classification current to inform the pse about its required power class (class 1, 2, 3, or 4). type 1 pses cannot provide enough power for a class4 pd. type 2 pses have additional voltage steps before switching on the pd. after an initial classification voltage pulse, the type 2 pse reduces the voltage below the mark threshold level (10 v) then raises it up again to the class event range. last, before switching on the dcdc it reduces the voltage again. this sequence is recognized by the si3406x and its pull down its nt2p pin to inform the application about the higher available power; otherwise, the application will need to operate in a reduced power consumption state (type 1) if the pse is incapable of delivering class 4 power. figure 2.4. powered device voltages 2.3 hotswap switch the internal hotswap switch (hssw) is turned on (conducting) when the poe interface voltage goes above v uvlo_r . it provides limited inrush current until the dcdc side capacitor is charged. the hotswap switch turns off (open) if voltage on the hssw switch (hso-vneg) is greater than v hssw_off . in overload, the hotswap switch goes into current-limiting mode with a current limit of i ovl . it will turn back on after twaithssw elap- ses and the dc-dc input capacitor is recharged, meaning the hso-vneg voltage is less than v hssw_on . the hotswap switch (if it is in the on state and conducting) can detect if the current is lower than i mpsth . in this case, the chip turns on mps pulse generation, which ensures that the pse will not disconnect. with the si34061, an external hotswap switch can be used to improve efficiency and reduce thermal stress in high current applications. for class 3 applications, using an external hotswap switch is recommended; for class 4, it is mandatory because the internal hotswap switch otherwise generates significant heat. when an external hotswap switch is used, intelligent switch control ensures that inrush cur- rent limiting and automatic mps request of the internal switch are still supported. si3406x family data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 6
2.4 hssw state machine the hssw operates as simple 4-state state machine: figure 2.5. hotswap switch 4-state machine note: internal signal names are shown in this figure, not to be confused with external pin names. for the below discussion, i load is the switch current, and v hssw is the voltage drop of the switch. in other words, v hssw = hso C vneg. all the voltage, current and time limits of the above diagram are typical values. off state hssw turn-on is controlled by uvlo, the undervoltage lockout feature. when uvlo is engaged, the hssw is off. in this state, the hssw is in idle mode, vneg and hso pins are disconnected. in normal operation, a complete detect/classification procedure pre- cedes the hssw turn-on, and the control of this sequence is implemented in the state machine logic of the chip. inrush state after the controller enables the hssw, the block starts operation in the inrush state. in this state the switch itself is not directly turned on, but operating in a closed-loop current limit mode to avoid high current peaks during the charging of the primary bypass cap of the dc to dc converter. if the v hssw voltage drops below 380 mv (meaning the bypass cap is 99% charged), the hssw will change state to on either in type1 classification immediately, or in type2 classification if the hssw has been in the inrush state for at least 80 ms. on state in on state, the hssw switch is directly turned on. the hssw circuit continuously monitors v hssw . hssw will change to overload state if v hssw voltage increases over 3.6 v for at least 140 s. overload state in overload state the hssw operates in closed-loop low current limit mode. if the v hssw voltage drops below 360 mv again, and the hssw has been in the overload state for at least 80 ms, the hssw will change back to the on state. 2.4.1 external hssw fet driver an external hssw fet may be used to improve thermal operation of an si34061 at very high power loading levels (the top end of class 4). with the si34061, the chip automatically detects if the exthsw pin is connected to vneg or to a fet gate at startup. if the external hotswap fet driver will not be used, the exthsw pin must be tied to vneg. for further information on using an external hssw fet, please refer to "an1130: using the si3406/si34061/si34062 poe+ and si3404 poe pd controller in isolated and non-isolated designs". si3406x family data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 7
2.5 dc to dc converter the dc-to-dc converter is current-controlled for easier compensation and more robust protection of circuit magnetics. the controller has the following features: ? high- and low-side feedback (supports buck and flyback topologies). ? <1 internal switching fet ? driver for optional synchronous rectification ? overcurrent detection ? low current detection ? cycle skipping at low current and short circuit conditions ? optional external switching fet driver (si34061) ? automatic non-overlap control swo erout fbl fbh v11 syncl drv 1.32v g mh 100s g ml 100s g mpeak 50s 1.32v i peak limit vdd drv non overlap driver 1:1072 comp clipping blanking time vdd r q q comp 270mv 50mv comp lpf isns osc c softs soft start v erout limit reset loop comp vpos i avg limit low current detect pd vdd or and slope compensation s short detect pd short detect vss vpos vdd figure 2.6. si3406x dc-dc converter when the internal switching fet is used with the converter, internal peak current detection is employed. when the extgd pin and an external fet are used with si34061, an external current sense resistor is used to measure the peak current connected to the swisns pin. changing that resistor allows the application to set the converter maximum peak current to protect the magnetic components (like the transformer) from saturation. feedback to the dcdc converter can be provided in three ways: ? high side, referenced to vpos, connected to fbh pin (buck converter) ? low side, referenced to vss, connected to fbl pin (nonisolated flyback) ? directly to erout pin by a voltage to current converter (isolated flyback) the erout pin provides current output (if fbl or fbh is used) and voltage input. also, the loop compensation impedance is connec- ted to erout. the active voltage range is v erout , which is proportional to the converter peak current. the converter startup is not configurable; soft start is accomplished by internal circuitry. soft start time is t softstart . the intelligent soft start circuit dynamically adjusts the soft start time depending on the connected load. si3406x family data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 8
2.5.1 average current sensing, overcurrent, and low-current detection the application average current is sensed by an external resistor (r sense ) connected between vss and isns. overcurrent is detected and triggered when the voltage on the sense resistor exceeds v isns_ovc . sizing the resistor allows the designer to set the overcurrent limit according to application needs. when overcurrent is triggered, the dcdc controller goes into reset until the overcurrent resolves. when the overcurrent is no longer present, the controller starts up again with softstart. this external sense resistor is also used to detect a low current situation. when the voltage on the sense resistor goes below v isns_lc , the dcdc controller disables the sync fet and the external hotswap switch, allowing very low current consumptionthe internal hots- wap switch then measures the chip current internally. if the average current is lower than the poe maintain power signature (mps) limit, and if automatic sleep mode is enabled, the chip turns on the mps generation. see the sleep mode section for further detail. 2.5.2 sync fet driver with the si3406x family, an optional synchronous rectifying fet may be used in place of an output rectifier diode for improved power conversion efficiency. a gate driver is provided for this purpose. the synchronous rectifying fet driver is enabled by default in si3406x configurations, but, if a synchronous fet is not used in the design, the syncl pin must not be connected (do not connect syncl to any power or ground rail). the synchronous rectifying fet driver is disabled only when the dcdc converter measures low average current (meaning lower than v isns_lc on isns). this ensures low sleep mode current consumption. 2.6 external hssw fet driver an external hssw fet may be used to improve thermal operation of an si34061 at very high power loading levels (the top end of class 4). with the si34061, the chip automatically detects if the exthsw pin is connected to vneg or to a fet gate at startup. if the external hotswap fet driver will not be used, the exthsw pin must be tied to vneg. for further information on using an external hssw fet, please refer to "an1130: using the si3406/si34061/si34062 poe+ and si3404 poe pd controller in isolated and non-isolated designs". 2.7 tunable oscillator the dcdc frequency can be fixed to 250 khz or tunable by an external resistor. the tuning resistor must be connected between the r freq pin and vpos. if r freq is shorted to vpos, the fixed frequency oscillator will provide the clock, f oscint , to the dcdc converter; otherwise, the resistor will determine the frequency as shown in the curve below. figure 2.7. r freq frequency selector diagram si3406x family data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 9
2.8 regulators the chip provides a 5 v output to power leds or optocouplers. this is a closed-loop regulator, which ensures accurate output voltage. the 5 v regulator is supplied by an internal 11 v open loop regulator, which also provides power for the external fet gate drivers. the 11 v regulator is supplied by a coarse regulator, which is also open-loop. with the si34061 and si34062, the vt15 pin can be used to supply this regulator from an optional auxiliary transformer winding. the advantage of doing so is additional power saving since the external fet drivers current is not generated from the poe 50 v but, rather, from a transformer-provided 12C16 v. the application must be designed to ensure that the absolute maximum rating voltage for the vt15 pin is not exceeded. 2.9 sleep mode the si3406, si34061, and si34062 have automatic (consumption-based) and non-automatic sleep modes. when sleepb is tied to ground, the automatic sleep mode is enabled, meaning that if the current consumption is lower than impsth, the chip will automatically generate mps pulses to the pse. if sleepb is tied to vdd, then it will not generate mps pulses, and the pse will disconnect if total application current consumption drops below 5C10 ma. for non-automatic sleep mode, tie sleepb high at initial startup (right after the hotswap switch turns on). the chip turns off automatic mode, but pulling sleepb low will force mps generation as long as the pin is held low. using this mode, the designer can control mps generation. 2.10 extended sleep mode in the si34062, an extended sleep mode is available which includes led, wake, and mode pin support. the led pin drives a light emitting diode to (for example) illuminate a button on the primary side of the application. the wake pin triggers wakeup, and the mode button controls if mps generation is enabled in sleep. in the si34062 case, nsleep is used to initiate sleep. the sleep mode is initiated by a negative transition on nsleep. it is latched at that negative transition event together with mode, so their status is kept until wakeup even if the input changes on these pins due to the secondary side losing power. mps generation is enabled if mode = 0 at the nsleep transition. the following figure shows the si34062 sleep mode behavior. chip sleep, dcdc off mode? chip awake, dcdc runs wake pos. edge nsleep neg.edge low high turn mps generation on figure 2.8. si34062 extended sleep mode behavior refer to figure 3.3 si34062 iso flyback application diagram on page 13 , which shows shows the connectivity for the si34062 with the extended sleep mode. si3406x family data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 10
2.11 external wall support the si3406x supports using a wide voltage range of external wall adapters as a primary or secondary supply. for details on options and supported modes of adapter connection, please refer to "an1130: using the si3406/si34061/si34062 poe+ and si3404 poe pd controller in isolated and non-isolated designs". asup vpos swo c r isns vss isns hso r asup v aux 100k si34061 vneg v neg v pos hso hso from pse 12v-57v figure 2.9. example auxiliary wall adapter connection si3406x family data sheet system overview silabs.com | building a more connected world. preliminary rev. 0.5 | 11
3. application examples the following diagrams demonstrate the ease of use and straightforward bom of the si3406x powered device ics. detailed reference designs are available in evaluation kit user guides. also refer to "an1130: using the si3406/si34061/si34062 poe+ and si3404 poe pd controller in isolated and non-isolated designs". rfreq rfreq vpos vss cin vpos rdet rdet ct1 ct2 sp1 sp2 rclass rclass erout fbl syncl swo vdd vneg si3406 vneg cdet vss vss vss vss rcomp ccomp cout r1 r2 syncfet vout c rsense isns hso vss ct1 ct2 sp1 sp2 figure 3.1. si3406 non-iso flyback application diagram rfreq rfreq vpos vss cin vpos rdet rdet ct1 ct2 sp1 sp2 rclass rclass erout vdd syncl swo vdd vneg si34061 vneg cdet vss vss rcomp1 ccomp1 cout syncfet vout c vin vin exthsw hso isns rsense vss vt15 vss gndi gndi exthsw vss rcomp2 ccomp2 tlv431 r2 r1 gndi gndi bias vss *gndi = isolated ground figure 3.2. si34061 iso flyback application diagram si3406x family data sheet application examples silabs.com | building a more connected world. preliminary rev. 0.5 | 12
rfreq rfreq vpos vss cin vpos rdet rdet ct1 ct2 sp1 sp2 rclass rclass erout vdd syncl swo vneg si34062 vneg cdet vss vss rcomp1 ccomp1 cout syncfet vout c hso isns rsense vss vt15 vss gndi gndi vss rcomp2 ccomp2 tlv431 r2 r1 gndi gndi vss gndi vss gndi vss gndi vdd vdd nsleep vdd 'wake' wake mode vout sleep gndi vout vout wake mode nsleep led bias nsleep wake mode vss vdd *gndi = isolated ground ct1 ct2 sp1 sp2 led figure 3.3. si34062 iso flyback application diagram si3406x family data sheet application examples silabs.com | building a more connected world. preliminary rev. 0.5 | 13
4. electrical specifications table 4.1. absolute maximum ratings 1 type description min max units voltage ct1Cct2 or sp1Csp2 C100 100 v vneg-vss, vpos- vneg, hso 2 , rdet 3 C0.7 100 v swo-vss C0.7 120 v isns, swisns C1 1 v low voltage pins: fbh 3 , erout, fbl, nsleep, rcl 2 , rfreq 3 , asup 3 , wake, mode, led C0.7 6 v mid voltage pins: syncl,vt15, extgd, exthsw C0.7 18 v other mid voltage pin: v11 C0.7 12 v peak current ct1, ct2, sp1, sp2, vpos Ctbd tbd a dc current 4 ct1, ct2, sp1, sp2 C0.2 0.2 a temperature storage temperature C65 150 c ambient operating temperature C40 85 note: 1. unless otherwise noted, all voltages referenced to vss. permanent device damage may occur if the maximum ratings are excee- ded. functional operation should be restricted to those conditions specified in the operational sections of this data sheet. expo- sure to absolute maximum rating conditions for extended periods may adversely affect device reliability. 2. voltage referenced to vneg. 3. voltage referenced to vpos. 4. higher dc current is possible in the application, but only utilizing external bridge diodes. refer to reference design documentation and an1130 for further details. si3406x family data sheet electrical specifications silabs.com | building a more connected world. preliminary rev. 0.5 | 14
table 4.2. recommended operating conditions symbol parameter (condition) min typ max unit v port |ct1 C ct2| or |sp1 C sp2| 2.7 57 v v hv_op vneg-vss, vneg-hso, vpos- vss 2.7 57 v v lv_op vpos referred low voltage pins: rfreq, rdet, fbh C5.5 0 v v lv_op vss referred low voltage pins: vdd, fbl, erout, asup, nsleep, nt2p, asup, wake, mode, led 0 5.5 v v oh_dig v oh of asup and nt2p relative to vss. 3 v v isns_op vss referred current sensing pins: isns, swisns C0.5 0.5 v v lv_op vneg referred low voltage pins: rcl 0 5.5 v v mv_op vss referred medium voltage pins syncl, extgd, exthsw 0 13 v v mv_vt15 vss referred medium voltage pin vt15 1 12 14.5 16.5 v i rect on chip rectifier current on ct1, ct2, sp1, sp2steady state 2 176 ma v rect on chip rectifier voltage @ 200 ma, 2 diodes 1.8 v i rect_pk peak rectifier current max 75 ms 5% duty cycle 3 231 ma i avg allowable continuous current on swo, vss, hso, vneg 600 ma i peak peak current on swo, vss, hso, vneg max 75 ms 5% duty cycle 683 ma note: 1. v mv_vt15 is relevant for si34061 and si34062 only when an external auxiliary winding from the primary side of the transformer is being used to improve power conversion efficiency. this can be left undriven, in which case an internal regulator will be used. 2. for class 3 and above operation, use external diode bridge rectifiers to bypass the internal input diode bridge rectifiers. 3. the ieee 802.3at specification allows for higher peak current for transients. si3406x family data sheet electrical specifications silabs.com | building a more connected world. preliminary rev. 0.5 | 15
table 4.3. electrical characteristics symbol parameter (condition) min typ max unit poe protocol detection v det detection voltage (at v port ) 2.7 10.1 v classification v reset classification reset (at v port ) 0 2.81 v v class classification voltage (at v port ) 14.5 20.5 v i portclass class 0 (r class > 681 ) 0 4 ma class 1 (r class = 140 @ 1%) 9 12 ma class 2 (r class = 75 @ 1%) 17 20 ma class 3 (r class = 48.7 @ 1%) 26 30 ma class 4 (r class = 33.2 @ 1 %) 36 44 ma type 2 classification v mark mark event voltage (at v port ) 6.9 10.1 v i mark mark event current 0.25 tbd 4 ma power on and uvlo v uvlo_r hotswap closed and converter on 37 v v uvlo_f hotswap open and converter off 32 v thermal characteristics t shd thermal shutdown 160 c t hyst thermal shutdown hysteresis 20 c on-chip transient voltage suppression/protection t prot tvs protection activation voltage (vpos-vneg) 100 v hotswap switch i inrush inrush current 100 170 200 ma i maxhssw maximum continuous operating cur- rent 600 ma v hssw_on switch on voltage 380 mv v hssw_off switch off voltage, hssw goes to overload cycle 3.5 v i ovl switch current limit in overload state 8.7 10.5 12.4 ma i mpsth mps signal request current level threshold 14 20 26 ma i ext_drv external hotswap driver peak current on exthsw pin 10 ma si3406x family data sheet electrical specifications silabs.com | building a more connected world. preliminary rev. 0.5 | 16
symbol parameter (condition) min typ max unit v ext_drv external hotswap driver voltage on exthsw pin 9 11 v t waithssw wait time in overload and type 2 inrush 80 96 116 ms r onhssw internal hotswap drain-source resist- ance while on 0.65 1.5 2.9 ? dc-dc i swopeak peak current limit of internal fet (swo pin) 2.1 2.7 a v extgd external fet driver voltage (extgd pin) 9 11 13 v i extgd external fet driver peak current (extgd pin) 500 ma f oscint using internal oscillator 250 khz f oscext using external oscillator, tunable on pin rfreq 100 500 khz duc output duty cycle of pwm tbd 75 % v dcdcuvlo dcdc uvlo level (minimum adapt- er voltage) 10.2 10.7 11.3 v v fbref fbh (referenced to vpos) and fbl (referenced to vss) reference volt- age 1.32 v v erout operating voltage range of error in- put 1 4 v v isns_ovc overcurrent limit voltage on isns (ref. to vss) C270 mv v isns_lc low current limit voltage on isns (ref. to vss) C30 mv v swisnsmax external fet current sense 240 mv t softstart startup time 4 ms r ondcdc internal dcdc switching fet drain- source resistance while on 0.9 1.2 ? regulators vt15 override internal regulator with transformer winding 13 16.5 v vdd high accuracy 5 v 4.85 5.1 5.46 v vdd ilim dc current limit of vdd 9.7 11.2 12.9 ma c reg filter capacitor on vdd and v11 100 nf i maxled led pin max current, reduces vdd ilim 5 ma i maxdo digital output max current (nt2p), reduces vdd ilim 2 2.5 ma power dissipation si3406x family data sheet electrical specifications silabs.com | building a more connected world. preliminary rev. 0.5 | 17
symbol parameter (condition) min typ max unit p intmax dc-dc max power internal fet 1.2 1.5 w p max total chip power tbd tbd w i portop operating current (v port 57 v; 250 khz) 3 4 ma package thermal characteristics ja-eff qfn20 44 c/w ja-eff qfn24 tbd c/w si3406x family data sheet electrical specifications silabs.com | building a more connected world. preliminary rev. 0.5 | 18
5. pin descriptions si3406 pinout (top view) si34061 pinout (top view) si34062 pinout (top view) fbh erout fbl vdd nsleep rdet sp2 rcl rfreq sp1 hso vpos ct2 ct1 vneg (epad) isns vss syncl nt2p v11 swo 5 6 7 8 9 10 16 15 1718 19 20 1 2 3 4 11 12 13 14 isns erout fbl vdd nsleep rdet sp2 rcl rfreq sp1 hso vpos ct2 ct1 vneg (epad) swisns vss syncl v11 swo 7 8 9 10 20 19 2122 23 24 2 3 4 5 13 14 15 16 11 12 1 6 exthsw asup 17 18 nt2p vt15 extgd fbh erout fbl vdd nsleep rdet sp2 rcl rfreq sp1 hso vpos ct2 ct1 vneg (epad) isns vss syncl v11 swo 7 8 9 10 20 19 2122 23 24 2 3 4 5 13 14 15 16 11 12 1 6 led wake 17 18 nt2p vt15 mode table 5.1. pin descriptions '06 pins '061 pins '062 pins name ref dir. vrange description 24 24 swisns vss i 0C0.5 external fet peak current sense resistor voltage input 20 1 isns vss i -0.5C0 chip average current sense resistor input 1 1 fbh vpos i 0C5 high side (vpos referred) dcdc feedback (buck converter) 2 2 2 erout vss io 0C5 error amplifier current output, compensation impedance input 3 3 3 fbl vss i 0C5 low side (ground referenced) dcdc feedback (flyback convert- er) 4 4 4 vdd vss o 0C5 5v regulator output 5 led vss o 0C5 output to drive sleep led 5 exthsw vneg o 0C11 external hotswap switch drive 6 wake vss i 0C5 wakeup from sleep mode 6 asup vss i 0C5 aux auxiliary adapter present 5 7 7 nsleep vss i 0C5 sleep, with pull-up, driven by open drain 6 8 8 rdet vpos io 0C100 detection resistor 7 9 9 hso vneg io 0C100 hotswap switch output 8 10 10 rcl vneg io 0C5 classification resistor 9 11 11 rfreq vpos io 0C5 oscillator frequency tuning resistor, tie to vpos to select de- fault freq 10 12 12 sp2 sp1 i 0 - 100 high-voltage supply input from spare pair; polarity-insensitive 11 13 13 sp1 sp2 i 0C100 high-voltage supply input from spare pair; polarity-insensitive 12 14 14 vpos io 0C100 rectified high-voltage supply positive rail 13 15 15 ct2 ct1 i 0C100 high-voltage supply input from main pair; polarity-insensitive 14 16 16 ct1 ct2 i 0 - 100 high-voltage supply input from main pair; polarity-insensitive si3406x family data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 19
'06 pins '061 pins '062 pins name ref dir. vrange description 15 17 17 nt2p vss o 0C5 type ii classification was successful 18 18 vt15 vss i 0C16.5 dcdc transformer bias winding input 16 19 19 syncl vss o 0C11 gate driver for synchronous rectification fet 17 20 20 v11 vss io 0C11 11 v regulator output for filter cap. 21 extgd vss o 0C11 external fet gate drive. when internal switching fet is in use, tie to vss. 21 mode vss i 0C5 controls mps and led switch behavior 18 22 22 swo vss o 0C120 internal dcdc switch output (nmos drain) 19 23 23 vss io 0 dcdc converter primary ground epad epad epad vneg io 0 rectified high voltage supply ground si3406x family data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 20
5.1 detailed pin descriptions table 5.2. circuit equivalent and description of die pads pin name detailed description circuit detail swisns external dcdc switching fet peak current sense resistor input. the maxi- mum current of the switching fet should correspond to voltage v swisn- smax . isns average current sense resistor input. the resistor value will set the maxi- mum allowed average current for the application. the overcurrent threshold voltage v isns_ovc . note that this pin voltage goes below vss. fbh high side dcdc feedback input. need to be tied to vpos when not used. see vfbref. erout dcdc converter error output; current out, voltage sense. loop compensating impedance should be connected here. i erout = (v fbh C v fbref ) x 50 a or i erout = (v fbl C v fbref ) x 50 a fbl low side dcdc feedback input. need to be tied to vss when not used. see v fbref si3406x family data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 21
pin name detailed description circuit detail vdd regulated 5 v relative to vss. there is no foldback characteristic, reaching vdd ilim the output voltage decreases. the regulator needs c reg external capacitance. led led driver output max current is i maxled wake wake-up input pin for sleep mode, used only in si34062. asup auxiliary supply adapter is present. enables the operation of the dcdc con- troller without poe supply being present. nsleep sleep function input, see description in sleep mode section. si3406x family data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 22
pin name detailed description circuit detail rcl classification resistor input. for class 0 this pin can be left floating. pin is active only at time of classification. rfreq used for adjusting the oscillator frequency. the frequency is inversely proportional to the value of the connected resis- tor. sp1, sp2 ct1, ct2 main power inputs, goes to diode bridge producing vpos and vneg. vpos, vneg main chip power output generated by the diode bridge. note that vneg (the epad on the bottom of the chip) also provides thermal relief. nt2p pin main function is digital output; it is low if type 2 classification was suc- cessful and the application is allowed to draw class 4 current. output current is i maxdo , but the load (e.g. an led) should connected to vdd not vss; otherwise, it can cause false operation. si3406x family data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 23
pin name detailed description circuit detail hso hotswap switch output. the switch shorts the vneg and hso pins, and in- cludes several other functions. see hotswap switch section for details. extgd, syncl extgd: optional external switch driver of the dc/dc converter. when the in- ternal switch is used this pin should be tied to vss. this driver controls the external switch with 10 v logic level, relative to vss. syncl: optional synchronous rectifier switch driver of the dc/dc converter. when not used the pin must be left floating. this driver controls the external synchronous switch with 10 v logic level, relative to vss. exthsw optional external hotswap switch output. the maximum current of the inter- nal hotswap switch is i maxhssw , for higher currents an external nmos fet should be used parallel to the internal hssw (vneg-hso). when extgd is not used the pin should be tied to vneg. this driver controls the external switch with 10 v logic level, relative to vneg. rdet the user has to tie the rdet resistor between this pin and vpos. during detection, a high voltage switch pulls down rdet to vneg. after detection, the reference block uses rdet as absolute chip current reference, forcing C750 mv relative to vpos, creating 30 a for the internal blocks. si3406x family data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 24
pin name detailed description circuit detail vt15, v11 vt15 is input for an optional 15 v supply generated by an auxiliary trans- former bias winding. if the bias winding voltage is lower than vt15, the in- ternal 15 v coarse regulator will provide the current for the 11 v regulator. the v11 pin is for filtering capacitor for the 11 v regulator. a capacitor of value c reg is required. mode mps mode control, used in si34062. swo dcdc converter switching transistor drain output, vmax = 120 v. vss dc-dc converter ground. si3406x family data sheet pin descriptions silabs.com | building a more connected world. preliminary rev. 0.5 | 25
6. packaging 6.1 package outline: si3406 the figure below illustrates the package details for the si3406. the table lists the values for the dimensions shown in the illustration. figure 6.1. 20-pin, qfn package table 6.1. package diagram dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.25 0.30 0.35 d 5.00 bsc. d2 2.60 2.70 2.80 e 0.80 bsc. e 5.00 bsc. e2 2.60 2.70 2.80 l 0.50 0.55 0.60 l1 0.00 0.10 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 si3406x family data sheet packaging silabs.com | building a more connected world. preliminary rev. 0.5 | 26
dimension min nom max note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vhhb-1. si3406x family data sheet packaging silabs.com | building a more connected world. preliminary rev. 0.5 | 27
6.2 land pattern: si3406 the figure below illustrates the land pattern details for the si3406. the table lists the values for the dimensions shown in the illustration. figure 6.2. 20-pin, qfn land pattern table 6.2. land pattern dimensions dimension max c1 4.70 c2 4.70 x1 0.35 x2 2.80 y1 1.00 y2 2.80 e 0.80 note: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60mm minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si3406x family data sheet packaging silabs.com | building a more connected world. preliminary rev. 0.5 | 28
6.3 package outline: si34061/62 the figure below illustrates the package details for the si34061/62. the table lists the values for the dimensions shown in the illustra- tion. figure 6.3. 24-pin, qfn package table 6.3. package diagram dimensions symbol min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.25 0.30 0.35 a3 0.20 ref d 5.00 bsc. e 0.65 bsc. e 5.00 bsc. si3406x family data sheet packaging silabs.com | building a more connected world. preliminary rev. 0.5 | 29
symbol min nom max d2 2.90 3.00 3.10 e2 2.90 3.00 3.10 l 0.35 0.40 0.45 k 0.20 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si3406x family data sheet packaging silabs.com | building a more connected world. preliminary rev. 0.5 | 30
6.4 land pattern: si34061/62 the figure below illustrates the land pattern details for the si34061/62. the table lists the values for the dimensions shown in the illus- tration. figure 6.4. 24-pin, qfn land pattern table 6.4. land pattern dimensions dimension mm c1 4.90 c2 4.90 x1 0.35 x2 3.10 y1 0.85 y2 3.10 e 0.65 note: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted 2. this land pattern design is based on the ipc-7351 guidelines solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 mm minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release 2. the stencil thickness should be 0.125 mm (5 mils) 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si3406x family data sheet packaging silabs.com | building a more connected world. preliminary rev. 0.5 | 31
7. top markings 7.1 si3406 top marking figure 7.1. si3406 top marking table 7.1. si3406 top marking explanation mark method: laser pin 1 mark: circle = 0.50 mm diameter (lower-left corner) font size: 2.0 point (28 mils) line 1 mark format: device part number si3406 line 2 mark format: device type a = device revision a g = extended temperature range m = qfn package line 3 mark format: tttttt manufacturing trace code (assigned at assembly) line 4 mark format: yy = year ww = work week assembly year assembly week si3406x family data sheet top markings silabs.com | building a more connected world. preliminary rev. 0.5 | 32
7.2 si34061 top marking figure 7.2. si34061 top marking table 7.2. si34061 top marking explanation mark method: laser pin 1 mark: circle = 0.50 mm diameter (lower-left corner) font size: 2.0 point (28 mils) line 1 mark format: device part number si34061 line 2 mark format: device type a = device revision a g = extended temperature range m = qfn package line 3 mark format: tttttt manufacturing trace code (assigned at assembly) line 4 mark format: yy = year ww = work week assembly year assembly week si3406x family data sheet top markings silabs.com | building a more connected world. preliminary rev. 0.5 | 33
7.3 si34062 top marking figure 7.3. si34062 top marking table 7.3. si34062 top marking explanation mark method: laser pin 1 mark: circle = 0.50 mm diameter (lower-left corner) font size: 2.0 point (28 mils) line 1 mark format: device part number si34062 line 2 mark format: device type a = device revision a g = extended temperature range m = qfn package line 3 mark format: tttttt manufacturing trace code (assigned at assembly) line 4 mark format: yy = year ww = work week assembly year assembly week si3406x family data sheet top markings silabs.com | building a more connected world. preliminary rev. 0.5 | 34
8. revision history revision 0.5 february, 2018 ? updated 2. system overview and 3. application examples . ? added theory of operation and application content. ? updated table 4.1 absolute maximum ratings 1 on page 14 , table 4.2 recommended operating conditions on page 15 , and table 4.3 electrical characteristics on page 16 . ? clarified multiple parameters. ? added 5.1 detailed pin descriptions . ? added 6. packaging including outline and land pattern. revision 0.1 august, 2016 ? initial release. si3406x family data sheet revision history silabs.com | building a more connected world. preliminary rev. 0.5 | 35
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